Silicon Labs /EFR32FG23A010F256GM40 /LCD_S /UPDATECTRL

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Interpret as UPDATECTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MANUAL)AUTOLOAD 0 (BACTRLWR)LOADADDR

LOADADDR=BACTRLWR, AUTOLOAD=MANUAL

Description

No Description

Fields

AUTOLOAD

Auto Load

0 (MANUAL): CLK_BUS register to CLK_PER register loads must be done manually with a write to CMD.LOAD.

1 (AUTO): CLK_BUS register to CLK_PER register loads will be started automatically after a write to the register in UPDATECTRL.LOADADDR is detected.

LOADADDR

Load Address

0 (BACTRLWR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to BACTRL. Use with UPDATECTRL.AUTOLOAD

1 (AREGAWR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to AREGA. Use with UPDATECTRL.AUTOLOAD

2 (AREGBWR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to AREGB. Use with UPDATECTRL.AUTOLOAD

3 (SEGD0WR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD0. Use with UPDATECTRL.AUTOLOAD

4 (SEGD1WR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD1. Use with UPDATECTRL.AUTOLOAD

5 (SEGD2WR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD2. Use with UPDATECTRL.AUTOLOAD

6 (SEGD3WR): Starts synchronizing registers from CLK_BUS to CLK_PER after a write to SEGD3. Use with UPDATECTRL.AUTOLOAD

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